搜索资源列表
simple_dual_port_ram_single_clock
- Simple Dual-Port RAM with different read/write addresses but single read/write clock
6
- 左单片机读取双口RAM中分配给右单片机的配置信息存储空间，右单片机读取双口RAM中分配给左单片机的配置信息存储空间，良但片即读取配置信息后可以按照配置信息对自身工作方式等进行设定，达到双机通信的目的，间接实现了一单片机对另一单片机的配置控制。-Left microcontroller reads the dual-port RAM allocated to the right microcontroller configuration information storage space, rig
C51_RAM
- C51下IDT7005双口RAM控制程序和原理图-C51 under IDT7005 dual-port RAM control procedures and schematics
RAM_VHDL
- 用VHDL描述了一个32KBit的独立的读写时钟、使能、地址的双口RAM，-VHDL descr iption of a 32KBit with independent read and write clock, enable, address the dual-port RAM,
rtl
- dual port RAM 4096x16
ram2
- 双口RAM驱动,此文档是有说明的哦，希望对大家有帮助-Dual-port RAM drive
idt723641
- VERILOG双端口驱动IDT的双扣RAM很好用的-VERILOG Twill the IDT dual-port RAM drive good use
dualram
- 双口RAM驱动程序，对于基于ARM 板子的嵌入式linux开发者，使用到双口RAM，可以在此驱动源码上修改成自己需要的。-Dual-port RAM driver board for ARM-based embedded linux developer, using the dual-port RAM, you can modify the source code in this drive into their needs.
IPRAM
- FPGA内置RAM,调用tools里面的IP核，生成一个双口的RAM，用来存储数据。然后可以用SignalTAP II查看波形或者数据。-FPGA built-in RAM, which is called IP core tools to generate a dual port RAM, used to store data. You can then view the waveform or use SignalTAP II data.
PCI9054
- PCI总线芯片PCI9054本地总线的FPGA控制逻辑。 硬件架构为PCI9054+双口RAM+FPGA。 使用USERo清中断。 该逻辑以在项目中应用。-PCI bus FPGA chip PCI9054 local bus control logic. Hardware architecture PCI9054+ dual-port RAM+ FPGA. Use USERo clear interrupts. The logic to apply in the pro
SDRAMping-pong-memory-structure
- 双口RAM 的乒乓存储结构（芯片型号CY7C09279） 应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging
Test_2_Port_RAM
- Quartus ii双口RAM模块的使用，包括源码、ram时序图以及测试报告-Use Quartus ii dual-port RAM modules, including source code, ram timing diagram and test reports
ADPUARTPDPRAM
- ad7606采集信号数据存入双口ram再通过串口发送出去。- ad7606 collected signal data stored in the dual port ram and then sent through the serial port.
635355963606373750
- 本文介绍了应用FPGA实现对高速A/D转换芯片的控制电路，介绍了这一控制的设计思想，并提出了通过双口RAM实现FPGA与慢速度的单片机进行双机数据通信处理的解决方案。- Data acquisition is an item of indispensable technology which is essential to the industrial control system. As the increasing need for speed performance of the da
dpram1_24_240
- 24X240 dual port ram
dpram1_24_1920
- 24x1920 dual port ram
cell_arch
- cell architecture for dual port ram
ug_ram_rom
- This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP c
Dual-port-RAM-data-acquisition
- 利用传统方法设计的高速数据采集系统由于集成度低、电路复杂，高速运行电路干扰大，电路可靠性低，难以满足高速数据采集工作的要求。应用FPGA可以把数据采集电路中的数据缓存、控制时序逻辑、地址译码、总线接口等电路全部集成进一片芯片中，高集成性增强了系统的稳定性，为高速数据采集提供了理想的解决方案。-Using traditional methods of high-speed data acquisition system design due to low integration, circuit
uart_ram
- 串口接收数据校样后存入双口ram,接收完整帧数据后，置中断，通知串口发送-After receiving proof serial data stored in dual port ram, receive a complete frame of data after the interrupt, serial port to send notifications